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copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. multi-output power supply with vcom amplifier for epd features single chip power management solution for e- paper displays input supply voltage range: 3.0~5.5v i 2 c series interface boost converter for positive rail base (hvinp) inverting buck-boost converter for negative rail base (hvinn) accurate voltage tracking between hvinp and hvinn: + 50mv integrated two power switches with soft-start control for source driver supply -pos: +15v/120ma -neg: -15v/120ma two charge pump for gate driver supply -dgvdd: +22v/20ma -dgvee:-22v/20ma accurate and adjustable vcom voltage for panel backplane biasing - -0.3 to -2.85v/100ma, 10mv per step -8-bit control programmable turn-on/turn-off timing in every output voltage remote temperature sensing pok output fault output enable input current limit protection over temperature protection fault events report in every output for easy de- bugging 1mhz fixed pwm frequency up to 85% efficiency for the boost internal soft start control available in tqfn5x5-32 package halogen and lead free available (rohs compliant) applications general description the APW7223 is a single chip, multi outputs pmic for e- paper displays. two pwm converters respectively gener- ate positive and negative voltages which are boosted to higher voltage by two charge pumps for both source and gate drivers. two integrated power switches are used to disconnect these pwm outputs from load in shutdown mode. all pwm and charge pump output voltages are adjustable by external resistors and their power on/off timings can be individually programmable via i 2 c interface. one accurate vcom voltage, for backplane biasing, is adjustable via i 2 c interface from -0.3v to -2.85v with 10mv per step. the vcom is capable of sourcing and sinking current, depending on panel condition, at lease 100ma. an external negative temperature coefficient(ntc) resis- tor is incorporated to sense remote temperature. this remote temperature sensing can be used to monitor the battery s surface temperature to avoid over heating. the temperature data is mapped from the voltage on ts pin according to a preset conversion table. approximately every 250 m s the APW7223 executes the voltage/tempera- ture conversion and stores the temperature date in reg- ister in two s complement format. the APW7223 is available in a space saving tqfn5x5 32-pin package and is specified over the -40 o c to +85 o c extended temperature range. e-paper displays
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 2 simplified application circuit 1mhz pwm boost 1mhz pwm inv positive charge pump negative charge pump vcom pos soft- start neg soft- start i 2 c interface thermal adc hvinp hvinn pos 15v neg -15v dgvdd +22v dgvee +22v ordering and marking information note: anpec lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with rohs. anpec lead-free products meet or exceed the lead-free requirements of ipc/jedec j - std-020d for msl classification at lead-free peak reflow temperature. anpec defines green to mean lead-free (rohs compliant) and halogen free (br or cl does not exceed 900ppm by weight in homogeneous material and total of br and cl does not exceed 1500ppm by weight). APW7223 handling code temperature range package code assembly material APW7223qb: xxxxx - date code package code qb : tqfn5x5-32 operating ambient temperature range i : -40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device apw 7223 xxxxx
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 3 symbol parameter rating unit in, inn, cen, en, pok, /flt, fbp, fbpg, fbng, ref, vdd, scl, sda, ts to gnd voltage -0.3 ~ 6.5 v vref to gnd voltage -0.3 ~ 4 v lxp, hvinp, pos, pgvdd, dp to pgnd -0.3 ~ 24 v lxn, hvinn, neg, pgvee, dn, pbkg, vcom to pgnd -24 ~ 0.3 v dgvdd to pgnd -0.3 ~ 40 v dgvee to pgnd -40 ~ 0.3 v pgnd to gnd voltage -0.3 ~ 0.3 v p d power dissipation internally limited w maximum junction temperature 150 o c t stg storage temperature -65 ~ 150 o c t sdr maximum lead soldering temperature (10 seconds) 260 o c absolute maximum ratings (note 1) pin configuration 1 dp 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 pgvdd fbpg dgvee pok dgvdd ref fbng p g v e e d n v d d s c l s d a v r e f t s e n /flt cen hvinn pgnd gnd vcom pos neg h v i n n l x n i n n h v i n p l x p p g n d f b p i n hvinn note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 4 thermal characteristics symbol parameter typical value unit q ja junction-to-ambient resistance in free air (note 2) 20 o c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. recommended operating conditions (note 3) symbol parameter range unit in, inn, vdd, scl, sda, ts to gnd voltage -0.3 ~ 5.5 v cen, en, pok, /flt, fbp, fbpg, fbng, ref to gnd voltage -0.3 ~ v in +0.3 v lxp, hvinp to pgnd voltage 12 ~ 18 v pos, pgvdd, dp to pgnd voltage -0.3 ~ v hvinp +0.3 v lxn, hvinn to pgnd voltage -20 ~ v in +0.3 v neg, pgvee, dn, vcom, pbkg to pgnd voltage -v hvinn -0.3 ~ 0.3 v dgvdd to pgnd -0.3 ~ 30 v dgvee to pgnd -30 ~ 0.3 v pgnd to gnd voltage -0.3 ~ 0.3 v lxp, lxn, inn, pgnd rms current -0.3 ~1.6 a t a ambient temperature -40 ~ 85 o c t j junction temperature -40 ~ 125 o c note 3: refer to the typical application circuit electrical characteristics unless otherwise specified, these specifications apply over v in =3.6v and t a = 25 o c. APW7223 symbol parameter test conditions min typ max unit input supply and reference voltage v in input voltage range 3 - 5.5 v in uvlo threshold 2.5 2.8 2.95 v in uvlo hysteresis - 0.15 - v i dd1 en=gnd and the shutdown bit=0 - 40 60 m a i dd2 in quiescent current v en =3.6v, no switching - 2 3.5 ma vdd input voltage 1.6 - 5.5 v vdd uvlo threshold v vdd rising 1.0 1.2 1.5 v vdd uvlo hysteresis - 50 - mv vdd quiescent current normal mode - 20 50 m a ref output voltage no load - 1.250 - v ref uvlo threshold ref rising - 1.0 1.2 v ref uvlo threshold - 50 - mv
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 5 electrical characteristics unless otherwise specified, these specifications apply over v in =3.6v and t a = 25 o c. APW7223 symbol parameter test conditions min typ max unit input supply and reference voltage vdd quiescent current normal mode - 20 50 m a ref output voltage no load - 1.250 - v ref uvlo threshold ref rising - 1.0 1.2 v ref uvlo threshold - 50 - mv refok high threshold ref rising - 1.5 - v refok low threshold ref falling - 1.1 - v ref load regulation 0 < i ref < 100 m a - 10 20 mv ref line regulation 3v < v in < 5.5v - 2 5 mv vref output voltage no load (10mv/step) 2.51 2.56 2.61 v vref output current 5 - - ma step-up regulator v hvinp output voltage range v in - 18 v operating frequency 850 1000 1150 khz oscillator maximum duty cycle 91 95 98 % fbp regulation voltage 1.238 1.250 1.262 v fbp load regulation 1ma < i pos < 200ma - -1 - % fbp line regulation v in = 3v to 5.5v -0.3 -0.08 0.3 %/v fbp input bias current v fbp =1.25v - - 100 na lxp on resistance i lxp = 0.2a - 250 500 m w lxp leakage current en=gnd, v lxp = 18v - - 20 m a lxp current limit duty cycle = 80% 1.5 1.8 - a soft-start period - 680 - m s inverting regulator inn input voltage range 3 - 5.5 v no switching - 80 - m a inn quiescent current switching - 0.5 - ma v hvinn output voltage range -18 - - v operating frequency 850 1000 1150 khz oscillator maximum duty cycle 91 95 98 % lxn on-resistance inn to lxn, i lxn = 0.2a - 250 - m w lxn leakage current in=3.6v, lxn= -18v - - 20 m a lxn current limit duty cycle = 80% 1.8 2.1 - a soft-start current limit - 500 - ma v pos -v neg regulation voltage -50 - 50 mv
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 6 electrical characteristics unless otherwise specified, these specifications apply over v in =3.6v and t a = 25 o c. APW7223 symbol parameter test conditions min typ max unit positive charge pump regulator hvinp-dp current limit 200 300 - ma oscillator frequency 400 500 600 khz fbpg regulation voltage 1.238 1.250 1.262 v fbpg line regulation v hvinp =12v to 18v - 0.05 0.2 %/v fbpg input bias current v fbpg = 1.25v -50 - 50 na dp on-resistance high i dp = 100ma - 20 - w dp on-resistance low i dp = -100ma - 24 - w soft-start period - 2.5 - ms negative charge pump regulator hvinn-dn current limit 200 300 - ma oscillator frequency 400 500 600 khz fbng regulation voltage -12 0 12 mv fbng line regulation v neg = -12v to -18v - 0.05 0.2 %/v fbng input bias current v fbng = 0v -50 - 50 na dn on-resistance high i dn = 100ma - 20 - w dn on-resistance low i dp = -100ma - 12 - w soft-start period - 2 - ms vcom input supply range v hvinn - -5 v hvinn quiescent current - 0.6 5 ma vcomp voltage high i vcom = 5ma - - -0.3 v vcomp voltage low i vcom = -5ma -2.85 - - v sourcing 100 - - ma vcom output current sinking 100 - - ma vcom tri-state leakage cen=gnd - - 1 m a sequence switches v pos pos output range tracks hvinp v in - 18 v pos on-resistance (hvinp-pos), i pos = 100ma - 0.5 1 w pos discharge resistance - 200 - w pos soft-start charge time - 2 - ms v neg neg output range tracks hvinn -18 - - v neg on-resistance (hvinn-neg), i neg = 100ma - 0.5 1 w neg discharge resistance - 150 - w neg soft-start charge time - 2 - ms pgvdd on-resistance (hvinp-pgvdd), i pgvdd = 30ma - 20 - w pgvee on-resistance (hvinn-pgvee), i pgvee = 30ma - 10 - w
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 7 electrical characteristics unless otherwise specified, these specifications apply over v in =3.6v and t a = 25 o c. APW7223 symbol parameter test conditions min typ max unit sequence switches dgvdd input voltage range - - 30 v dgvdd discharge resistance - 100 - w dgvee input voltage range -30 - 0 v dgvee discharge resistance - 150 - w vcom discharge resistance - 1000 - w fault protection fbp fault threshold v fbp falling 0.94 1.00 1.05 v fbpg fault threshold v fbpg falling 0.94 1.00 1.05 v hvinn fault threshold v hvinn rising -v hvinp *0.85 -v hvinp *0.80 -v hvinp *0.75 mv fbng fault threshold v fbng falling 200 250 330 mv fault debounce - 250 - m s thermal shutdown hysteresis = 30 o c - 160 - o c temperature sensor monotonicity guaranteed 10 - - bits temperature resolution lsb - 0.5 - o c conversion time - 19 - m s conversion rate conf: d7=d6=0 - 250 - conv / m s programmable vcom calibrator vcom-dac voltage resolution 8 - - bits vcom-dac differential nonlinearity monotonic over temperature -1 - +1 lsb vcom-dac zero-scale error 0 +1 +2 lsb vcom-dac full-scale error -4 - +4 lsb memory factory setting - 80 - hex memory program voltage supply to /flt pin 7.00 7.15 7.3 v memory write cycles 8 - - times memory write time need to confirm tbd - - ms control logic input low voltage (in) en, cen - - 0.4 v input high voltage (in) en, cen 1.2 - - v pok logic-low output voltage i pok = -6ma - - 0.4 v /flt leakage current v flt = 5.5v - - 1 m a /flt output low voltage i flt = 6ma - - 0.4 v
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 8 electrical characteristics unless otherwise specified, these specifications apply over v in =3.6v and t a = 25 o c. APW7223 symbol parameter test conditions min typ max unit i 2 c interface input capacitance sda, scl - 5 - pf v il input low voltage sda, scl - - 0.3*v vdd v v ih input high voltage sda, scl 0.7*v vdd - - v sda sink current v sda = 0.4v 6 - - ma f scl scl frequency dc - 400 khz t high scl high time 600 - - ns t low scl low time 1300 - - ns t r sda, scl rise time c bus = total bus line capacitance (pf) 20+ 10xc bus - 300 ns t f sda, scl fall time c bus = total bus line capacitance (pf) 20+ 10xc bus - 300 ns t hd:sta start hold time 10% of sda to 90% of scl 600 - - ns t su:sta start setup time 600 - - ns t hd:dat data input hold time 0 - - ns t su:dat data input setup time 100 - - ns t su:sto stop setup time 600 - - ns t buf bus free time 1300 - - ns input spike suppression sda, scl - - 50 ns t timeout sda reset low time (note 5) - - 50 ms note 4: guaranteed by design, not production tested. note 5: holding the sda line low for a time greater than t timeout causes the device to reset sda to the idle state of the serial bus communication (sda set high). t hd,sta t f t low t r t high t hd,dat t su,dat t su,sta t su,sto t buf scl sda
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 9 pin no. name function 1 dp regulated charge pump driver for gvdd. connect to flying cap. 2 pgvdd supplies the hvinp voltage for the positive charge pump. connect as shown in figure 1. 3 fbpg feedback input for gvdd. threshold = 1.25v. 4 dgvdd connect the output of the positive charge pump to dgvdd as shown in figure 1. 5 pok power ok. open drain output that goes low when all outputs have reached regulation. 6 dgvee connect the output of the negative charge pump to dgvee as shown in figure 1. 7 ref ic voltage reference. 1.25v. connect an 1 m f cap to this pin. 8 fbng feedback input for gvee. threshold = 0v. 9 pgvee supplies the hvinn voltage to the negative charge pump for the gvee output. connect as shown in figure 1. 10 dn regulated charge pump driver for gvee. connect to flying cap. 11 vdd logic supply input for the i 2 c. bypass to gnd through a minimum 0.1 m f capacitor. 12 scl i 2 c serial clock input. 13 sda i 2 c serial data input/output. 14 vref filter pin for 2.5v internal reference to adc. 15 ts thermistor input pin. connect a 10k ntc thermistor and a 7k w linearization resistor between this pin and gnd. 16 en enable pin. logic high initiates power-up sequencing. logic low initiates power down sequencing. 17 /flt fault indicator. open drain output goes low during a fault condition. 18 cen vcom enable. logic high enables vcom output. logic low causes the load on the vcom output to be discharged 19 hvinn input power for the neg voltage rail. connect the output of the inverting converter to this pin. 20 pgnd power ground. 21 gnd analog ground. connected this pin pgnd. 22 vcom vcom output. 23 pos positive source driver output voltage. 24 neg negative source driver output voltage. 25 hvinn input power for the neg voltage rail. connect the output of the inverting converter to this pin. 26 lxn dc-dc inverting converter inductor/diode connection. 27 inn inverting converter power input. 3v to 5.5v. 28 hvinp input power for the pos voltage rail. connect the output of the step-up converter to this pin. 29 lxp step-up converter inductor/diode connection. 30 pgnd power ground. 31 fbp feedback pin for hvinp output. threshold = 1.25v 32 in ic power input. exposed pad die substrate/thermal pad. connected this pad to hvinn. pin description
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 10 operating waveforms power on-1 v in v hvinp v vcom v hvinn 1 4 ch1: v in , 5v/div, dc time: 10ms/div ch2: v hvinp , 10v/div, dc ch3: v hvinn , 10v/div, dc ch4: v vcom , 2v/div, dc v in =5v, c1=c5=22 m f , l1=l2=4.7 m h, r1=330k w , r2=30k w , c2=c6=4.7 m f, c11=1 m f 2 3 power off-1 v in v hvinp v vcom v hvinn 1 4 ch1: v in , 5v/div, dc time: 500ms/div ch2: v hvinp , 10v/div, dc ch3: v hvinn , 10v/div, dc ch4: v vcom , 2v/div, dc 2 3 v in =5v, c1=c5=22 m f , l1=l2=4.7 m h, r1=330k w , r2=30k w , c2=c6=4.7 m f, c11=1 m f power on-2 v in v pos v neg 1 ch1: v in , 5v/div, dc time: 20ms/div ch2: v pos , 10v/div, dc ch3: v neg , 10v/div, dc 2 3 v in =5v, c1=c5=22 m f , l1=l2=4.7 m h, r1=330k w , r2=30k w , c2=c6=4.7 m f, c3=c4=1 m f power off-2 v in v pos v neg 1 ch1: v in , 5v/div, dc time: 200ms/div ch2: v pos , 10v/div, dc ch3: v neg , 10v/div, dc 2 3 v in =5v, c1=c5=22 m f , l1=l2=4.7 m h, r1=330k w , r2=30k w , c2=c6=4.7 m f, c3=c4=1 m f the test condition is v in =5v, t a = 25 o c unless otherwise specified.
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 11 operating waveforms the test condition is v in =5v, t a = 25 o c unless otherwise specified. power on-3 v in v dgvdd v dgvee 1 ch1: v in , 5v/div, dc time: 50ms/div ch2: v dgvdd , 10v/div, dc ch3: v dgvee , 10v/div, dc 2 3 v in =5v, c1=c5=22 m f , l1=l2=4.7 m h, r1=330k w , r2=30k w , c13=c14=c15=1 m f, r11=330k w , r12=20k w power off-3 v in v dgvdd v dgvee 1 ch1: v in , 5v/div, dc time: 100ms/div ch2: v dgvdd , 10v/div, dc ch3: v dgvee , 10v/div, dc 2 3 v in =5v, c1=c5=22 m f , l1=l2=4.7 m h, r1=330k w , r2=30k w , c13=c14=c15=1 m f, r11=330k w , r12=20k w load transient-1 v hvinp i hvinp 1 ch1: v hvinp , 1v/div, offset=15v time: 200 m s/div ch2: i hvinp , 100ma/div, dc 2 v in =5v, c1=22 m f , c2=4.7 m f, l1=4.7 m h, r1=330k w , r2=30k w , i hvinp =0ma-200ma-0ma load transient-2 v hvinn i hvinn 1 ch1: v hvinn , 1v/div, offset=-15v time: 200 m s/div ch2: i hvinp , 100ma/div, dc 2 v in =5v, c5=22 m f , c6=4.7 m f, l2=4.7 m h, i hvinn =0ma-200ma-0ma
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 12 block diagram and typical application circuit pgvdd dp dgvdd dgvee dn v gvdd = +22v fbng(0v) ref cen en pok /flt vdd scl sda gnd ts vcom regulated charge pump fbpg regulated charge pump 20ma pgvee v gvee = -20v 1.25v i 2 c interface vcom register and dac enable control and fault logic otp memory in lxp hvinp neg hvinn inn lxn pgnd fbp (1.25v) pos 3v~5.5v input 3v~5.5v input 1mhz pwm boost pos soft- start neg soft- start 1mhz pwm inv v pos = +15v 120ma v neg = -v pos 120ma power rail output control temp adc vref 2.56v (1.25v) c1 22 f l1 4.7 h c2 4.7 f c8 2.2 f c7 1 f c13 1 f r1 330k c5 22 f l2 4.7 h c6 4.7 f c4 1 f c3 1 f r2 30k r11 330k 10k ncp18xh103f03rb r8 27k r7 430k r12 20k c14/1 f c15 1 f c9 1 f c10 1 f c12 1 f r6 10k r5 10k d1 d1 d2 d3 d4 i 2 c bus vref 10k//24k r13 c11 1 f r15 in note : forced 3.3v to vref pin for v com : -0.3v to -3.59v
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 13 power sequence t1 t2 t3 t4 hvinp hvinn dgvee dgvdd pok pos en neg t5 t6 t7 t8 512ms 1 5 4 3 2 16ms pulling the en pin high initiates an adjustable pre-set power-up sequence while pulling the en pin low initiates an adjustable pre-set power-down sequence. the power-up/power-down sequence and timing between rails are deter- mined by the user s values programmed into the timing registers via i 2 c before the en pin is pulled high/low. the desired sequence and timing between rails contained in the timing registers can also be stored in the mtp, such that desired timing information is loaded into the timing registers at power-up. figure 2 shows a sample power-up and power-down sequence. the sequence and timing between the power rails for both power-up and power-down are accomplished by programming the desired t1-t8 times into the timing registers and/or storing the desired t1-t8 times into the mtp. 1. the hvinp power rail begins its soft-start sequence once en is driven high. 2. the hvinn power rails begin its soft-start sequence once hvinp soft-start period has expired. 3. each power rail will begin to power-up at a time depending on the values stored in the timing registers(t1-t4). 4. pok is asserted high after fbng, neg, pos and fbpg have all exceeded 80% of their regulation voltages and all the corresponding power rails soft-start periods have expired. 5. once en goes low, each power rail is actively discharged at a time depending on the values stored in the timing registers (t5-t8). approximately 512 ms after en is driven low, hvinp and hvinn are powered down but not actively discharged.
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 14 function description the APW7223 is a single chip power supplies designed to for portable e-paper displays applications. two high efficiency dc/dc boost converters generate +/-15v rails which are boosted to +/- 22v by two change pumps to provide the gate driver supply panel. two tracking ldos create the +/-15v source driver supplies which support up to 120ma of output current. all rails are adjustable through the i 2 c interface to accommodate specific panel requirements. main control loop under-voltage lockout an under-voltage lockout function prevents the device from operating if the input voltage on v in is lower than approxi- mately 2.8v. the device automatically enters the shut- down mode if the voltage on v in drops below approxi- mately 2.65v. this under-voltage lockout function is imple- mented in order to prevent the malfunctioning of the converter. over-temperature protection (otp) the over-temperature circuit limits the junction tempera- ture of the APW7223. when the junction temperature ex- ceeds 160 o c, a thermal sensor turns off the both power mosfets, allowing the devices to cool. the thermal sen- sor allows the converters to start a soft-start process and regulate the output voltage again after the junction tem- perature cools by 30 o c. the otp designed with a 30 o c hysteresis lowers the average junction temperature (t j ) during continuous thermal overload conditions, increas- ing the life time of the device. vcom accurate back-plane biasing is provided by a linear am- plifier and can be adjusted either by the i 2 c interface. the vcom driver can source or sink current depending on panel condition. for automatic vcom adjustment in production line, vcom can be set from -0.3v to -2.85v with 8 bits control through the serial interface. the power switch is inte- grated to isolate vcom driver. soft-start the APW7223 has a built-in soft-start to control the out- put voltage rise during start-up. during soft-start, an in- ternal ramp voltage, connected to the one of the positive inputs of the error amplifier, raises up to replace the ref- erence voltage (1.25v typical) until the ramp voltage reaches the reference voltage. then the voltage on fbx regulated at reference voltage. pulse skipping modulation mode (psm) the APW7223 is a fixed frequency pwm peak current mode control step-down converter. at light loads, the APW7223 will automatically enter in pulse skipping mode operation to reduce the dominant switching losses. these controls get low quiescent current, help to main- tain high efficiency over the complete load range. temperature sensor the APW7223 allows the user to take full control of the temperature sensing circuit at the expense of additional i 2 c read/writes and associated software over-head in the main processor. it is designed for use with host proces- sors that can read and write to multiple registers using standard i 2 c protocol. fault protection the under-voltage protection circuit monitors the voltage on fbx (v fbx ) by under-voltage (uv) comparator to protect the pwm converter against short-circuit conditions. when the v fbx falls below the falling uvp threshold (20% of ref), a fault signal is generated and the device turns off all mosfets. the converter shuts down and the output is latched to be floating. the APW7223 will initials a soft- start process until re-cycle en or v in .
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 15 function description (cont.) the APW7223 completely disconnects the loads from the input when in shutdown mode. in most boost con- verters the external rectifying diode and inductor form a dc current path from the battery to the output. this can drain the battery even in shutdown if a load were con- nected at the boost converter output. the APW7223 inte- grated 4 isolated switch at pos/neg/pgvdd/pgvee. when these switches turn off during shutdown there is no dc path from the input to pos/neg/pgvdd/pgvee. load disconnected
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 16 application information input capacitor selection because buck converters have a pulsating input current, a low esr input capacitor is required. this results in the best input voltage filtering, minimizing the interference with other circuits caused by high input voltage spikes. also, the input capacitor must be sufficiently large to sta- bilize the input voltage during heavy load transients. for good input voltage filtering, usually a 4.7 m f input capaci- tor is sufficient. it can be increased without any limit for better input-voltage filtering. ceramic capacitors show better performance because of the low esr value, and they are less sensitive against voltage transients and spikes compared to tantalum capacitors. place the input capacitor as close as possible to the input and gnd pin of the device for better performance. inductor selection for high efficiencies, the inductor should have a low dc resistance to minimize conduction losses. especially at high-switching frequencies the core material has a higher impact on efficiency. when using small chip inductors, the efficiency is reduced mainly due to higher inductor core losses. this needs to be considered when select- ing the appropriate inductor. the inductor value deter- mines the inductor ripple current. the larger the inductor value, the smaller the inductor ripple current and the lower the conduction losses of the converter. conversely, larger inductor values cause a slower load transient response. a reasonable starting point for setting ripple current, d il, is 40% of maximum output current. the recommended inductor value can be calculated as below: i l(max) = i out(max) + 1/2 x d il to avoid saturation of the inductor, the inductor should be rated at least for the maximum output current of the con- verter plus the inductor ripple current. l sw in out out i f v v 1 v l d ? ? ? ? ? - 3 output voltage setting in the adjustable version, the output voltage is set by a resistive divider. the external resistive divider is con- nected to the output, allowing remote voltage sensing as shown in typical application circuits . a suggestion of maximum value of r2 is 400k w to keep the minimum current that provides enough noise rejection ability through the resistor divider. the output voltage can be calculated as below: ? ? ? ? ? + = ? ? ? ? ? + = 2 r 1 r 1 25 . 1 2 r 1 r 1 v v ref out output capacitor selection the current-mode control scheme of the APW7223 al- lows the use of tiny ceramic capacitors. the higher ca- pacitor value provides the good load transients response. ceramic capacitors with low esr values have the lowest output voltage ripple and are recommended. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 17 i 2 c programming the APW7223 s i 2 c slave address is a hard-coded 7 bit address 90h(1001000). the APW7223 supports the following write and read protocol and contains 17 registers. ... ... a6 a5 a4 a0 r/w ack r7 r6 r5 ... r0 ... ... d7 ack d6 d5 ... d0 ack slave address start register address 0 0 0 0 data stop scl sda figure 1. the write protocol of i 2 c interface writing to the APW7223 ... ... a6 a0 r/wack r7 r0 ack slave address start register address 0 0 scl sda .. ... 0 repeated start a6 ... a0 r/w 1 ack 0 ... ... d0 ack 0 stop d7 slave address slave drives the data master drives ack and stop figure 2. the read protocol of i 2 c interface reading from the APW7223
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 18 register address (hex) r/w name power on default 1 00 read only external temperature register n/a 2 01 r/w temperature offset (for calibration) 00h 3 02 r/w configuration register n/a 4 03 r/w enable register 00 5 04 r/w vcom_adjust 80h 6 05 read only fault register n/a 7 06 r/w programming control register 00h 8 07 r/w t1 timing register 1eh 9 08 r/w t2 timing register 3ch 10 09 r/w t3 timing register 5ah 11 0a r/w t4 timing register 78h 12 0b r/w t5 timing register 1eh 13 0c r/w t6 timing register 3ch 14 0d r/w t7 timing register 5ah 15 0e r/w t8 timing register 78h 16 0f read only product revision id 00h 17 10 read only product id 4dh register address map register address: 00h field name external temperature[7:0] data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name sign temperature data read/write r/w r/w r/w r/w r/w r/w r/w r/w power on default field name bit definition externaltemperature[7:0] temperature readout: 1000 0001: -127 o c 1111 1110: -2 o c 1111 1111: -1 o c 0000 0000: 0 o c 0000 0001: +1 o c 0000 0010: +2 o c 0111 1111: +127 o c when the configuration register (02h) has been written 01h , meaning the temperature conversion is shutdown, reading from this externaltemperature register will return a nack. register definition
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 19 register address: 01h field name tempoffset[7:0] data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name sign temperature offset code read/write r/w r/w r/w r/w r/w r/w r/w r/w power on default 0 0 0 0 0 0 0 0 field name bit definition tempoffset[7:0] for some reason the user may want to set a temperature offset from the temperature readout. temperature offset selection 1111 0110: -10 o c 1111 1110: -2 o c 1111 1111: -1 o c 0000 0000: 0 o c 0000 0001: +1 o c 0000 0010: +2 o c 0000 1010: +10 o c register definition register address: 02h field name configuration[7:0] data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name shutdown read/write r/w power on default reserved 0 field name bit definition configuration[0:0] 0h : the APW7223 temperature immediately begins a temperature conversion and performs subsequent temperature conversion approximately every 250us. 01h : the APW7223 temperature conversion is shut down. the internal ntc circuit and adc bias is disabled. register address: 03h field name enable[7:0] data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name vcom_en en read/write r/w r/w power on default reserved 0 0 field name bit definition enable[1:0] 00: v com and all outputs are disabled. 01: v com is disabled, the other outputs is enabled. 10: v com is enabled, the other outputs is disabled (note) 11: v com and all outputs are enabled. note: because hvinn is disabled, there is no voltage to supply the v com , resulting v com no output voltage too.
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 20 register address: 04h field name vcom_adjust[7:0] data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name vcom voltage code read/write r/w r/w r/w r/w r/w r/w r/w r/w power on default 1 0 0 0 0 0 0 0 bit definition field name vcom voltage adjustment vcom_adjust[7:0] vref=open(vvref=internal 2.56v) 0000 0000: -0.300v 0000 0001: -0.310v 0000 0010: -0.320v 1000 0000: -1.58v 1111 1111: -2.850v vref=forced 3.3v 0000 0000: -0.3000v 0000 0001: -0.3129v 0000 0010: -0.3258v 1000 0000: -1.9514v 1111 1111: -3.5900v register definition register address: 05h field name fault[7:0] data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name pok ot hvinn_ fault hvinp_ fault pos_ fault neg_ fault gvdd_ fault gvee_ fault read/write r/w r r r r r r r power on default field name bit definition fault[7:0] the pok bit= 1 indicates all outputs voltages have risen above their pok thresholds; otherwise, there is at least one fault occurrence. the ot bit= 1 indicates over temperature has occurred. the hvinn_fault bit= 1 indicates the hvinn voltage is not good, and uv or sc is likely happening on it. the hvinp_fault bit= 1 indicates the hvinp voltage is not good and uv or sc is likely happening on it. the pos_fault bit= 1 indicates the pos voltage is not good and uv or sc is likely happening on it. the neg_fault bit= 1 indicates the neg voltage is not good and uv or sc is likely happening on it. the gvdd_fault bit= 1 indicates the gvdd voltage is not good and uv or sc is likely happening on it. the gvee_fault bit= 1 indicates the gvee voltage is not good and uv or sc is likely happening on it.
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 21 register address: 06h field name programmingcontrol[7:0] data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name timing dvr read/write r/w r/w power on default reversed 0 0 field name bit definition programcontrol[1:0] this register is used to control a multiplexer which determines the timing t1~t8 and vcom voltage are programmed by either the registers(eq. timing registers and/or vcom_adjust) or by the otp(one-time programmable memory) values. the bit timing and dvr can be separately written and read. when writing 1 to the timing and/or dvr bit, the t1~t8 timing and/or vcom voltage are programmed according to the current values stored in those timing registers(08h~0fh registers) and/or vcom_adjust register. when writing 0 to the timing and/or dvr bit, the t1~t8 timing and/or vcom voltage are programmed according to the current values stored in the otp memory. furthermore, in the meantime writing (note 1) to the t1~t8 timing registers and/or vcom_adjut register will rewrite the otp memory s values. the otp memory can be rewritten for several times: 8 times rewriting for vcom voltage . 2 times rewriting for each t1~t8 timing. when timing or dvr bit is 0 and you are writing 08h~0fh or 04h registers, you will alter the timgings or vcom voltage s default values. when the otp memory is run out, those default values will not be altered. note 1: in the otp memory rewriting process, the APW7223 needs a 7.15v voltage to be supplied to the /flt pin, otherwise otp values will not be altered. register definition register address: 07h~0eh field name timing[7:0] data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name timing code read/write r/w r/w r/w r/w r/w r/w r/w r/w power on default various values among 08h~0fh register, see bit definition below field name bit definition timing[7:0] the t1~t8 timing is programmable by writing following value into corresponding register to meet your application. 0000 0000=0ms 0000 0001=1ms 0000 0010=2ms 0000 0011=3ms 0000 0100=4ms 1111 1111=255ms the power on default value of t1 (07h register) and t5 (0bh register) is 1eh the power on default value of t2 (08h register) and t6 (0ch register) is 3ch the power on default value of t3 (09h register) and t7 (0dh register) is 5ah the power on default value of t4 (0ah register) and t8 (0eh register) is 78h
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 22 register address: 0fh field name product revision id[7:0] data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name id code read/write r r r r power on default reserved 0 0 0 0 field name bit definition product revision id[3:0] this register stores the version code: first version: 00h second version: 01h third version: 02h the eighth version: 07h register definition register address: 10h field name product id[7:0] data bit d7 d6 d5 d4 d3 d2 d1 d0 bit name product id code read/write r r r r r r r r power on default 0 1 0 0 1 1 0 1 field name bit definition product id[7:0] read only, product id= 4dh
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 23 layout considerations for all switching power supplies, the layout is an impor- tant step in the design; especially at high peak currents and switching frequencies. if the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. the input capacitor c1 and c2 should be placed close to the in/inn and gnd. connecting the capacitor and in/ inn-gnd with short and wide trace without any via holes for good input voltage filtering. the distance between in/ gnd to capacitor less than 2mm respectively is recommended. 2. to minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the sw pin to minimize the noise coupling into other circuits. 3. the output capacitor should be place closed to vout and gnd. 4. since the feedback pin and network is a high imped- ance circuit the feedback network should be routed away from the inductor. the feedback pin and feedback net- work should be shielded with a ground plane or trace to minimize noise coupling into this circuit. 5. a star ground connection or ground plane minimizes ground shifts and noise is recommended.
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 24 package information tqfn5x5-32 d e pin1 a b a1 a3 nx aaa c d2 e 2 pin 1 corner e k l s y m b o l min. max. 0.80 0.00 0.18 0.30 3.50 3.80 0.05 3.50 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tqfn5x5-32 0.35 0.45 3.80 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.138 0.150 0.138 0.014 0.018 0.70 0.150 0.028 0.002 0.50 bsc 0.020 bsc 0.20 0.008 k 4.90 5.10 0.193 0.201 4.90 5.10 0.193 0.201 0.08 0.003 aaa note : 1. followed from jedec mo-220 whhd-4.
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 25 carrier tape & reel dimensions h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 application a h t1 c d d w e1 f 330.0 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 -0.20 1.5 min. 20.2 min. 12.0 0.30 1.75 0.10 5.5 0.10 p0 p1 p2 d0 d1 t a0 b0 k0 tqfn 5x5 4.0 0.10 8.0 0.10 2.0 0.10 1.5+0.10 -0.00 1.5 min. 0.6+0.00 -0.40 5.35 0.20 5.35 0.20 1.00 0.20 (mm) package type unit quantity tqfn5x5-32 tape & reel 2500 devices per unit
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 26 taping direction information tqfn5x5-32 user direction of feed classification profile
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 27 profile feature sn-pb eutectic assembly pb-free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) (t s ) 100 c 150 c 60-120 seconds 150 c 200 c 60-120 seconds average ramp-up rate (t smax to t p ) 3 c/second max. 3 c/second max. liquidous temperature (t l ) time at liquidous (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak package body temperature (t p )* see classification temp in table 1 see classification temp in table 2 time (t p )** within 5 c of the specified classification temperature (t c ) 20** seconds 30** seconds average ramp-down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. classification reflow profiles table 2. pb-free process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm C 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 220 c 3 2.5 mm 220 c 220 c reliability test program test item method description solderability jesd-22, b102 5 sec, 245 c holt jesd-22, a108 1000 hrs, bias @ t j =125 c pct jesd-22, a102 168 hrs, 100 % rh, 2atm, 121 c tct jesd-22, a104 500 cycles, -65 c~150 c hbm mil-std-883-3015.7 vhbm R 2kv mm jesd-22, a115 vmm R 200v latch-up jesd 78 10ms, 1 tr R 100ma
copyright ? anpec electronics corp. rev. a.2 - may., 2016 APW7223 www.anpec.com.tw 28 customer service anpec electronics corp. head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 2f, no. 11, lane 218, sec 2 jhongsing rd., sindian city, taipei county 23146, taiwan tel : 886-2-2910-3838 fax : 886-2-2917-3838

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